A prior art SRAM memory circuit 50 is now described with reference to FIG. 1A. The SRAM memory circuit 50 includes first and second columns 52 and 54. The first column 52 includes memory cell 51 with a bitline BL0 and complementary bitline BLB0 associated therewith. The second column 54 includes memory cell 53 with bitline BL1 and complementary bitline BLB1 associated therewith. The column selection circuit 60 includes a PMOS transistor M1 with its source coupled to complementary bitline BLB0, its drain coupled to node INN, and its gate biased by control signal CTRL1. PMOS transistor M2 has its source coupled to bitline BL0, its drain coupled to node INP, and its gate biased by control signal CTRL1.
The column selection circuit 60 further includes a PMOS transistor M3 has its source coupled to complementary bitline BLB1, it drain coupled to node INN, and its gate biased by control signal CTRL2. PMOS transistor M4 has its source coupled to bitline BL1, its drain coupled to node INP, and its gate biased by control signal CTRL2.
Nodes INN and INP serve as the outputs of the column selection circuit 60 and the inputs to sense amplifier 55. In operation, one column 52 or 54 is selected by the column selection circuit 60 while the other column 52 or 54 is unselected. In the example operation state shown in FIG. 1A, column 52 is selected while column 54 is deselected. This is accomplished by control signal CTRL1 going low to turn on bitline select transistors M1 and M2, while control signal CTRL2 goes high or remains high to turn off bitline select transistors M3 and M4.
In an ideal case, as can be seen in FIG. 1B, when bitline BL0 and complementary bitline BLB0 are selected by transistors M1 and M2 being turned on where BL0 is to output a logic 1 and BLB1 is to output a logic 0, the voltage at node INP remains at VDD, while the voltage at node INN falls, with the difference between the two being Vdiff.
However, operation of the prior SRAM memory circuit 50 is not necessarily ideal. Although transistors M3 and M4 are turned off, there is a parasitic capacitance CP1 between the source of transistor M4 and node INP. As can be seen in FIG. 1B, since cell 53 store “0” value so BL1 discharges and due the parasitic capacitance CP1 between BL1 and INP node, node INP does not remain at VDD, but discharges which results in loss of effective Vdiff. The discharge current on BL1 through MEMCELL2 discharges INP due to the CP1 parasitic capacitor. Thus, the difference Vdiff between the voltages at INP and INN reduces by ΔV. This may cause an error when the bit lines BL0 and BLB0 are read.
This is an undesirable situation. Therefore, further development in the area of SRAM memory circuits is needed.